1. Field of the Invention
The present invention relates to non-volatile digital memory, and more particularly, to FLASH EPROM memory incorporating novel floating gates having reduced lateral dimensions.
2. Description of Related Art
FLASH EPROM memory is a class of non-volatile storage integrated circuits. In general, FLASH EPROMS have the capability of electrically erasing, programming, or reading a memory cell on a chip. Generally, a FLASH EPROM includes a floating gate and a control gate which form an electrical connection. A FLASH EPROM operates by charging or discharging electrons in the floating gate of the memory cell in a capacitive manner. The floating gate is formed of a conductive material, typically made of polysilicon, which is insulated from the channel of the transistor by a layer of oxide or other insulating material, and insulated from the control gate or word-line of the transistor by a second layer of insulating material.
The act of charging the floating gate is termed a Aprogram@ step for a FLASH EPROM. The program step may be accomplished through so-called hot electron injection by establishing a large positive voltage between the control gate and the source. The act of discharging the floating gate is called the Aerase@ function for a FLASH EPROM. The erase function is typically carried out by an F-N tunneling mechanism between the floating gate and the source of the transistor (source erase) or between the floating gate and the substrate (channel erase).
Due to increasing memory demands, a need exists to further reduce the size of memory devices, such as FLASH EPROMs. Reducing the cell size of memory devices increases performance and reduces power consumption.
Several devices have been developed with reduced cell size. One such device is described in AA Low Voltage Operating Flash Memory Cell with High Coupling Ratio Using Horned Floating Gate with Fine HSG,@ by Kitamura et al., 1998 Symposium on VLSI Technology Digest of Technical Papers. Another example of a memory device with reduced cell size is described in AA 0.24-Fm Cell Process With 0.18-Fm Width Isolation and 3D Interpoly Dielectric Films for 1-GB Flash Memories@ by Kobayashi et al., IEEE 97-275 (1997).
Reducing the size of a memory cell has led to memory cells with certain disadvantages including overbearing floating gates, or intermediate structures formed during the manufacturing of the floating gate, which degrade the tunnel oxide layer. The formation of sharp comers on the floating gate also leads to charge leakage.